Field of the Invention
The invention relates to synchronization when transferring data from asynchronous to synchronous domains.
Description of the Related Art
The transfer of a signal from an asynchronous domain to a synchronous domain involves a synchronizer circuit. Every synchronizer circuit has a certain probability of entering a metastable state. Metastability refers to a circuit, such as a flip-flop, whose output is unstable and may oscillate between a logical 0 and a logical 1 or remain at a voltage level between a logical 0 and a logical 1. The circuit typically settles to either the 0 state or the 1 state but not necessarily the correct state.
When in a metastable state, a synchronizer takes extra time to resolve the metastability, which can reduce system performance. FIGS. 1A and 1B illustrate the classic solution to deal with metastability that passes the asynchronous signal 101 through a synchronizer circuit 103 formed by a series of flip-flops 104 (FIG. 1B) clocked by a clock 105 associated with the synchronous domain 107. The synchronizer circuit 103 waits out the metastable state, if any, and supplies the synchronized output 106. The asynchronous logic function 109 supplies the asynchronous signal 101. The asynchronous logic function can be any function generating the asynchronous signal. For example, the asynchronous signal 101 can indicate that an instruction (e.g., a multiplication) has completed execution, or that a data packet has arrived, or that a condition exists such as a battery warning or thermal warning requiring action be taken.
Referring to FIG. 2, the asynchronous signal arrival time t1 of asynchronous signal 201 as referenced to the rising (or falling) edge of the clock signal can be at any time between two rising edges of the clock signal. As shown in FIG. 2, the arrival time is indicated by the asynchronous signal transitioning from a low level to a high level at time t1. There is no relation between the arrival time t1 of the asynchronous signal and the timing of the synchronous domain. As shown in FIG. 3, the probability distribution of t1 arriving at any particular time is uniform or flat. Thus, the probability of the arrival time t1 is the same for all values of t1:0≦t1≦T. The well-known formula for Mean Time Between Failures (MTBF) assumes uniform distribution of the arrival time as well.
The probability of metastability occurring can be calculated as W/T where W is the forbidden time window in which the asynchronous signal should not arrive or the metastable state can be entered. In an example shown in FIG. 3, W is shown as a particular set up time prior to the rising edge 301 of the clock signal. The value and location of W is a function of the particular synchronizer circuit utilized.
Reducing the likelihood of metastable states occurring can reduce failure rates and improve system performance.